The present invention relates to a semiconductor memory device having a primary memory cell array, a primary decoder which produces a first cell selection signal for accessing the primary memory cell array, an auxiliary memory cell array, and an auxiliary decoder which produces a second cell selection signal for accessing the auxiliary memory cell array.
An example of the prior art concerning a remedy for defects in a semiconductor memory device is shown in FIG. 1. In the figure, reference symbol MMCA denotes a primary memory cell array, symbol SMCA an auxiliary memory cell array, and symbol P a PROM. An address (DA0-DA3) of a defective cell and the presence/absence (ES) of a defective cell are programmed in the PROM. Symbol IB denotes an input buffer, symbols PD0 and PD1 pre-decoders, symbol MD a main decoder, and symbol AC an address compare circuit. FIG. 1 shows the case where an address signal A0-A3 is decoded by the pre-decoders PD0 and PD1 and the main decoder MD to select any one of sixteen word lines W0 to W15. The pre-decoders PD0 and PD1 pre-decode the bits A0, A1 and A2, A3 of the address signal to output pre-decode signals B0-B3 and C0-C3, respectively. These pre-decode signals are further decoded by the main decoder MD to select one of the word lines W0 to W15. The main decoder MD includes NOR circuits N0 to N15. The NOR circuit has two input terminals from which the pre-decode signals are received and one control terminal to which an output signal of the address compare circuit AC is supplied.
In the case where the primary memory cell array MMCA includes no defective cell, the PROM is programmed such that the signal ES is "1". With this programming, the output of the address compare circuit AC always takes "0" to enable the main decoder MD so that the primary memory cell array MMCA is accessed. At this time, since a word line WS takes "0" the auxiliary memory cell array SMCA is not accessed.
On the other hand, in the case where the primary memory cell array MMCA includes a defective cell, for example, in the case where a memory cell connected to the word line W0 is defective, the PROM is programmed such that the signal ES is "0" and the defective cell address signal DA0-DA3 indicates an address of the defective word line or are "0000" in the case of the present example. With this programming, when the address signal A0-A3 is "0000" the output of the address compare circuit AC takes "1" to disable all the NOR circuits in the main decoder MD so that the primary memory cell array MMCA is not accessed. On the other hand, since the word line WS takes "1" at this time, the auxiliary memory cell array is accessed in lieu of the primary memory cell array. In the case where the address signal is other than "0000" the output of the address compare circuit AC takes "0" to enable the main decoder MD so that the primary memory cell array is accessed. Namely, a memory chip containing a defective cell can be remedied in such a manner that the auxiliary memory cell array is accessed in the case where an address indicating the defective cell is inputted while the primary memory cell array is accessed in the other cases.
One example of references concerning defect remedy technique for semiconductor memory devices is an article written on pp. 1000-1002 of The Journal of The Institute of Electronics and Communication Engineers of Japan, September 1982.
In the above prior art, the number of logic stages up to the word lines is 3 in the case where the primary memory cell array is accessed. On the other hand, in the case where the auxiliary memory cell array is accessed, the number of logic stages is 4 since the signal passes through the address compare circuit AC. Further, since the output of the address compare circuit AC is connected to all the second-stage decoders, a load imposed on the address compare circuit becomes very large and a delay time becomes long. Accordingly, there is an inconvenience that an access time becomes long when the auxiliary memory cell array is accessed. Therefore, the conventional defect remedy technique could not successfully be applied to a field of technique in which a high speed operation is required.
JP-A-5-234395 laid open on Sep. 10, 1993 has disclosed a defect remedy circuit for memory device provided with an address compare circuit which is formed using transfer gates.
JP-A-3-228300 laid open on Oct. 9, 1991 has disclosed a semiconductor memory circuit provided with a substitutional address judgement circuit. The substitutional address judgement circuit takes no logic combination with an internal address signal or the substitutional address judgement circuit itself determines a substitutional address, thereby making it possible to reduce a time from an external address signal to an internal selected address signal.
JP-A-63-302499 laid open on Dec. 9, 1988 corresponding to Dutch Patent Application No. 8701085 filed on 1987 has disclosed a memory device provided with a redundant decoder and a redundant memory cell array. An input signal of the redundant decoder is selected by transfer gates and fuses so that the redundant memory cell array is accessed by a selected signal portion.